Installing Xilinx libraries in Active-HDL This interface allows users to run mixed VHDL, Verilog and System Verilog (design) simulation using Active-HDL as a default simulator. This application note has been verified on Active-HDL 10.3 and Xilinx ISE 14.7. This document describes how to start Active-HDL simulator from Xilinx ISE Project Navigator to run behavioral and timing simulations. Starting Active-HDL as the Default Simulator in Xilinx ISE Introduction
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